Programmable logic switches are devices for on/off-controlling logic switches (e.g., transistors) according to data that are held by a memory. In general, programmable logic switches are used for, for example, programmable logic devices such as FPGAs (field programmable gate arrays) in which logic operational circuits or interconnection circuits need to be reconfigured. For example, such programmable logic device includes plural wirings and a connection unit (plural connection units) for switching connection/disconnection of these wirings. The programmable logic switches may be used in such connection unit.
Programmable logic switches that are used in conventional FPGAs employ a volatile memory such as an SRAM. Therefore, the data stored in the memory are lost when the power is shut off. This means a problem that data need to be read from a separately provided memory area when the power is turned on again. In general, each cell of an SRAM is composed of six transistors, which raises a problem that the chip area of an FPGA increases as the number of SRAM cells used therein increases.
Programmable logic switches that employ a nonvolatile flash memory are known as devices capable of solving this problem. Each memory cell of an FPGA disclosed in U.S. Pat. No. 6,002,610-B includes a first nonvolatile memory device and a second nonvolatile memory device which are connected to each other in series. The gates of the first nonvolatile memory device and the second nonvolatile memory device are connected to a common line (control voltage line). A connecting point of the first nonvolatile memory device and the second nonvolatile memory device acts as an output node Q of the memory cell. A switching transistor of the programmable logic switch and an n-MOS transistor are connected to the output node Q of the memory cell. While the memory cell is in an operation mode, one of the first nonvolatile memory device and the second nonvolatile memory device is in an erased state and the other is in a written state. A voltage 0 V is applied to the source of one of the first nonvolatile memory device and the second nonvolatile memory device, and a power supply voltage (e.g., 3 V) is applied to the source of the other nonvolatile memory device. As a result, the switching transistor is made on or off depending on which of the first nonvolatile memory device and the second nonvolatile memory device is in a written state.
While the memory cell is in a programming mode, a first write voltage (7 V) is applied to the gates of the first and second nonvolatile memory devices, a second write voltage (4 V) is applied to the source of one, to be rendered into a written state, of them, and 0 V is applied to the source of the other. At this time, the n-MOS transistor is turned on and 0 V is applied to the node Q via the n-MOS transistor. As a result, a potential difference occurs between the source and the drain of a nonvolatile memory device to be rendered into a written state and data is written to it.
While the memory cell is in an erasing operation mode, a first erase voltage (−6 V) is applied to the gates of the first and second nonvolatile memory devices and 0 V is applied to the sources of the first and second nonvolatile memory devices. At this time, the n-MOS transistor is turned on and a second erase voltage (4 V) is applied to the node Q via the n-MOS transistor. As a result, the potential difference between the drain and the gate of the first nonvolatile memory device and that of the second nonvolatile memory device are 10 V. Electrons are pulled out of the storage films of the two nonvolatile memory devices using these potential differences.
However, each memory cell of the FPGA disclosed in U.S. Pat. No. 6,002,610-B has the following problems. First, to enable writing to only one nonvolatile memory device, each memory cell is provided with the n-MOS transistor. This results in increase in chip area and chip cost. Second, to apply a power supply voltage to the gate of the switching transistor of a memory cell, it is necessary to charge up also the drain junction capacitance of the n-MOS transistor, which results in increase in voltage transmission time, that is, reduction in memory cell operation speed. Third, while a memory cell is in the erasing operation mode, a second erase voltage (4 V) is applied to the gate of the switching transistor from the node Q. Since the substrate voltage of the switching transistor is 0 V, the gate insulating film of the switching transistor should be thick enough not to be broken when the second erase voltage is applied to its gate. Where a high second erase voltage is used for erasing data from the nonvolatile memory devices, the gate insulating film of the switching transistor is made thick and the operation speed of the switching transistor is thereby lowered. Fourth, different voltages are applied to the source of the n-MOS transistor while each memory cell is in the erasing operation mode and while it is in the programming mode. Furthermore, to turn on the n-MOS transistor, the potential difference between its source and gate need to be set higher than or equal to the threshold voltage Vth. Therefore, it is necessary to apply different voltages to the gate of the n-MOS transistor in the erasing operation mode and in the programming mode. Thus, power sources of such plural voltages are necessary.